Non-volatile memory (“NVM”) devices are fabricated in a large variety of structures, including but not limited to polysilicon floating gate, as shown in FIG. 2A, and Nitride Read Only Memory (“NROM”), as shown in FIG. 2B. Floating gate devices usually include a conducting charge trapping layer (e.g., composed of polysilicon), as shown in FIG. 2A, and thus usually provide only one charge storage region NROM devices, on the other had, may include a dielectric charge storage layer (e.g. composed of silicon oxide), as shown in FIG. 2B, and thus may support multiple charge storage regions (e.g. one near the cell's source junction and one near the cells drain junction). Each charge storage region of an NVM device may be considered to be a separate NVM cell or unit.
For purposes of producing mass data storage devices (e.g. Flash Memory Cards/Sticks, Multimedia Card, etc.), NVM cells are usually organized into and fabricated as part of a large matrix of cells referred to as an array. Depending upon which one of the many known array architectures and operating methodologies is used, each cell in an array may be addressable, programmable, readable and/or erasable either individually or as part of a group/block of cells. Most cell array architectures, including virtual ground arrays, which are well known in the field, include the feature of a multiplicity of repeating segments formed into rows and columns. According to some exemplary array architectures, such as a virtual ground array, each array segment may include a cell area formed of four segmented cell bit lines, an even select area, and an odd select area. The even select area may be located at one end of the cell area and may include a segmented even contact bit line and two select transistors connecting the even contact bit line with the even cell bit lines of the segment. The odd select area may be located at the opposite end of the cell area and may include a segmented odd contact bit line and two select transistors connecting the odd contact bit line with the odd cell bit lines of the segment. An NVM array may additionally include one even contact connected to the even contact bit lines of two neighboring even select areas, one odd contact connected to the odd contact bit lines of two neighboring odd select areas and alternating even and odd metal lines connecting to the even and odd contacts, respectively
As is well known, an NVM cell's logical state may be defined and determined by its threshold voltage (“Vt”), the gate to source/drain voltage at which the cell begins to significantly conduct current. Each cell or charge storage region of a multi-charge storage region NVM device may be associated with a difference threshold voltage and thus may store a unique logical value. Each cell or each charge storage region may be operated (i.e. programmed, erased or read) from a separate terminal or set of terminals of its respective device. The operation of multi-charge storage region NVM devices is well known in the art. The preceding and proceeding discussion relating to the operation of an NVM cell may apply either to the operation of a single charge storage region of a single charge storage region device or to the operation of each charge storage region of a multi-charge storage region device.
For each NVM cell, different threshold voltage values are associated with different logical states, and a NVM cell's threshold voltage level may be a function of the amount of charge (e.g electrons or holes) stored in the charge storage region of the cell. FIG. 1A shows a voltage distribution graph depicting possible threshold voltage distributions of a binary non-volatile memory cell, wherein vertical lines depict boundary cell threshold voltage Vt values associated with each of the cell's possible logical states. For example, cells having Vt Lower than EV level may be considered erased verified. Cells having Vt Higher than PV may be considered program verified. These two limits define logical states associated with the completion of programming and erase sequences that may be performed on a cell. A Program sequence of programming pulses may be used to drive the Vt of a cell higher than PV, while an erase sequence may be used to drive the cell's Vt lower than EV. Also visible in FIG. 1A is a vertical line designating a Read Verify (RV) level which is often used during a reading operation. More specifically, if during reading a cell's Vt is above the RV level, the cell is considered programmed, and if the cell's Vt is below RV, the cell is considered not to be programmed
FIG. 1B shows a voltage distribution graph depicting possible threshold voltage distributions in the charge storage region of a multi-level non-volatile memory cell (“MLC”), wherein one set of vertical lines depict boundary values correlated with each of the cell's possible Program Verify Threshold Voltages (PV00, PV01, etc.), and another set of vertical lines depict boundary values correlated with the Read Verify level of each of the cell's possible program states (RV00, RV01, etc.).
Various methods for programming (i.e. injecting charge into the charge storage regions) and/or erasing (i.e. removing charge from a charge storage region) of individual cells within an NVM array are known. For the most part, the amount of charge stored in a charge storage region of an NVM cell may be increased by applying one or more programming pulses to the cell, while conversely, the amount of charge in the charge storage region of a cell may decrease by applying one or more erase pulses to the gate terminal of an NVM cell, thus forcing the release of trapped charges from the cell's trap region and from the cell's trap interfaces. Alternatively, an erase process may include injecting charge of opposite polarity rather than a physical removal of charge. For example, if a programming process includes injecting electrons into a cell's charge traps, a corresponding erase process may include the injection of holes into the traps. The opposite charges may recombine and or cancel the effect of each other.
More specifically, when discussing an erase procedure for one or more NVM cells in an NROM virtual ground array, an erase step may include the application of a strong negative voltage pulse to the gates of one or more cells (e.g. −7V), the application of a positive voltage to the drains of the cells (e.g. +3V to +7V), and allowing the sources of the cell to float. For cell's being erased, the charges stored in their respective trap regions near their drain junctions, slightly over the channel, may be sunk in the drains of the cells being erased (or being recombined with the hole injection).
Groups or sets of cells within an NVM array may be programmed and/or erased concurrently. The group or set of NVM cells may consist of cells being programmed to (or erased from) the same logical state, or may consist of cells being programmed to (or erased from) each of several possible states, such as may be the case with cells in an MLC array. Since not all cells have the same susceptibility to being programmed and/or being erased, cells within a set of cells receiving programming or erasing pulses may not program or erase at the same rate. Some cells may reach a target program state, or an erased state, before other cells in the same set of cells that are receiving programming or erasing pulses concurrently.
Methods used for operating NVM cells (e.g. programming, reading, and erasing) use one or more reference structures such as reference cells to provide reference levels (i.e. PVs, EVs). Each of the one or more reference structures may be compared against a memory cell being operated in order to determine a condition or state of the memory cell being operated. Generally, in order to determine whether an NVM cell is at a specific state, for example erased, programmed, or programmed at one of multiple possible program states within a multi-level cell (“MLC”), the cell's threshold level is compared to that of a reference structure whose threshold level is preset and known to be at a voltage level associated with the specific state being tested for. Comparing the threshold voltage of an NVM cell to that of a reference cell is often accomplished using a sense amplifier. Various techniques for comparing an NVM's threshold voltage against those of one or more reference cells, in order to determine the state(s) of the NVM's cells, are well known.
When programming an NVM cell to a desired state, a reference cell with a threshold voltage set at a voltage level defined as a “program verify” level for the given state may be compared to the threshold voltage of the cell being programmed in order to determine whether a charge storage area or region of the cell being programmed has been sufficiently charged so as to be considered “programmed” at the desired state. If after a programming pulse has been applied to a cell, it has been determined that a cell has not been sufficiently charged in order for its threshold voltage to be at or above a “program verify” level (i.e. the threshold voltage of the relevant reference cell) associated with the target program state, the cell is typically hit with another programming pulse to try to inject more charge into its charge storage region. Once a cell's threshold value reaches or exceeds the “program verify” level to which it is being programmed, no further programming pulses may need to be applied to the cell. The same general principle of operation applies when erasing one or more cells, with the exception that erase pulses, rather than programming pulses, are applied to the cell.
Immediately after fabrication, and especially after multiple programming/erase cycles, each NVM cell's susceptibility to programming and erasing is different from that of any other NVM cell and continues to change over the life the of the cell. FIG. 3 shows a graph indicating an exemplary distribution of erase pulse voltage values required to induce an erased state in each of a set of NVM cells within each of multiple array segments of an exemplary NVM array such as the array shown in FIG. 4.
There is a need in the field of NVM production for improved methods, circuits and systems of erasing one or more NVM cells.